1. Field
The subject innovation relates generally to testing integrated circuits, and more particularly to systems and method for testing high voltage analog integrated circuits and pins prior to final printed circuit board assembly using BIST (built-in self-test) techniques.
2. Background
Multi-layer printed circuit boards (PCBs) and integrated circuits (ICs) are common in a wide array of electrical technologies and applications. The multi-layer PCBs and non-lead frame ICs can make efficient use of ever shrinking electrical packages, and reduce the overall resources necessary to produce an electrical component or set of components. However, testing the components can be difficult, due to a lack of connections between ICs accessible via probes. Moreover, the separation between the pins can be on the order of 0.1 mm, and using larger boards can result in undesirable consequences, such as larger products, increased trace pitch, and so forth. Typically, a large quantity of manufacturing and field faults in circuit boards are due to solder joints, imperfections in board connections, or the bonds and bond wires from IC pads to pin lead frames.
FIG. 1 illustrates an example standard test access port and boundary scan architecture (commonly called a JTAG interface) in accordance with an aspect of the subject specification. The JTAG interface 100 shown can be used for accessing sub-blocks of integrated circuits, and/or debugging embedded systems. In addition, the JTAG interface 100 can be used to transfer data into non-volatile memory. In general, JTAG interfaces 100 can provide convenient “back-door” access into ICs and electrical systems.
Current ICs typically have internal registers that are linked together in sets of scan chains. External manipulation of the scan chains enables testing of the combinational logic in the IC after it is mounted on a PCB, and/or possibly while in a functioning system. When combined with a built-in self-test (BIST), the JTAG scan chains enable a low overhead, embedded solution to testing an IC for certain static faults (e.g., shorts, opens, logic errors, etc.).
As illustrated, the JTAG interface 100 includes a test data in (TDI) 102, a test data out (TDO) 104, a test clock (TCK) 106, and a test mode select (TMS) 108. In addition, the JTAG interface 100 can include a test reset (not shown). The JTAG protocol (e.g., IEEE 1149.1) is a serial communication system, as can be appreciated based on its single data line (e.g., TDI). One bit of data is transferred per TCK 106 clock pulse at the TDI 102 and TDO 104 pins, respectively.
Typically, the scan chain mechanism does not provide for diagnosing or testing timing, temperature or other dynamic operational errors that may occur. In addition, the JTAG interface 100 is limited to digital ICs and some low voltage analog ICs (e.g., under five volts), and does not cover high voltage (HV) analog circuits. Consequently, it would be desirable to have an onboard automated technique for identifying errors in HV analog circuits prior to final assembly.